DE0-Nano Development Board

By Terasic Inc. 239

DE0-Nano Development Board

Terasic's DE0-Nano board provides a compact-sized FPGA development platform suited for prototyping circuit designs such as robots and "portable" projects. The board is designed to be used in the simplest possible implementation, targeting the Cyclone IV device up to 22,320 LEs.

The DE0-Nano has a collection of interfaces including two external GPIO headers to extend designs beyond the DE0-Nano board, on-board memory devices including SDRAM and EEPROM for larger data storage and frame buffering, as well as general user peripheral with LEDs and push-buttons.

The advantages of the DE0-Nano board include its size and weight, as well as its ability to be reconfigured without carrying superfluous hardware, setting itself apart from other general purpose development boards. In addition, for mobile designs where portable power is crucial, the DE0-Nano provides designers with three power scheme options including a USB mini-AB port, 2-pin external power header, and two DC 5 V pins.

Featured Device: Cyclone® IV EP4CE22F17C6N FPGA

  • 22,320 logic elements (LEs)
  • 594 embedded memory (K bits)
  • 66 embedded 18 x 18 multipliers
  • 4 general-purpose PLLs
  • 153 maximum FPGA I/O pins


  • On-board USB-Blaster circuit for programming
  • FPGA Serial Configuration Device (EPCS)
  • Two 40-pin headers (GPIOs) provide 72 I/O pins
  • Two 5 V power pins, two 3.3 V power pins, and four ground pins
  • One 26-pin header provides 16 digital I/O pins and 8 analog input pins to connect to analog sensors, among others
  • 32 MB SDRAM
  • 2 Kb I²C EEPROM
  • 8 green LEDs
  • 2 debounced pushbuttons
  • 4-position DIP switch
  • ADI ADXL345, 3-axis accelerometer with high resolution (13-bit)
  • A/D Converter, NS ADC128S022, 8-channel, 12-bit A/D converter
  • On-board 50 MHz clock oscillator

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