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74ALVCH16903DLRG4

74ALVCH16903DLRG4
Mfr. #:
74ALVCH16903DLRG4
Descripción:
IC UNIV BUS DVR 12BIT 56SSOP
Ciclo vital:
Nuevo de este fabricante.
Ficha de datos:
74ALVCH16903DLRG4 Ficha de datos
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74ALVCH16903DLRG4 más información 74ALVCH16903DLRG4 Product Details
Atributo del producto
Valor de atributo
Tags
74ALVCH16903D, 74ALVCH16903, 74ALVCH1690, 74ALVCH169, 74ALVCH1, 74ALVCH, 74ALVC, 74ALV, 74AL, 74A
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC UNIV BUS DVR 12BIT 56SSOP
***eco
12-BIT UNIVERSAL BUS DRIVER
***as Instruments
This 12-bit universal bus driver is designed for 2.3-V to 3.6-V VCC operation. The SN74ALVCH16903 has dual outputs and can operate as a buffer or an edge-triggered register. In both modes, parity is checked on APAR, which arrives one cycle after the data to which it applies. The YERR\ output, which is produced one cycle after APAR, is open drain. MODE selects one of the two data paths. When MODE is low, the device operates as an edge-triggered register. On the positive transition of the clock (CLK) input and when the clock-enable (CLKEN\) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition of CLK and when CLKEN\ is high, only data set up at the 9A-12A inputs is stored in their internal registers. When MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs. 11A/YERREN\ serves a dual purpose; it acts as a normal data bit and also enables YERR\ data to be clocked into the YERR\ output register. When used as a single device, parity output enable (PAROE\) must be tied high; when parity input/output (PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and PAROE\ is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When used in pairs and PAROE\ is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903. A buffered output-enable (OE\) input can be used to place the 24 outputs and YERR\ in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operation of the device. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16903 is characterized for operation from 0C to 70C.
Parte # Descripción Valores Precio
74ALVCH16903DLRG4
DISTI # 74ALVCH16903DLRG4-ND		IC UNIV BUS DVR 12BIT 56SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)		Limited Supply - Call
    74ALVCH16903DLRG4
    DISTI # 595-74ALVCH16903DLRG    		Universal Bus Functions 3.3-V 12-Bit Univ Bus Driver
    RoHS: Compliant    		0
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      Disponibilidad
      Valores:
      Available
      En orden:
      1500
      Ingrese la cantidad:
      El precio actual de 74ALVCH16903DLRG4 es solo de referencia, si desea obtener el mejor precio, envíe una consulta o envíe un correo electrónico directo a nuestro equipo de ventas [email protected]
      Precio de referencia (USD)
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      Debido a la escasez de semiconductores a partir de 2021, el precio inferior es el precio normal antes de 2021. Envíe una consulta para confirmar.
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