SN74ABT853DBRE4

SN74ABT853DBRE4
Mfr. #:
SN74ABT853DBRE4
Descripción:
Bus Transceivers 8 to 9-Bit Parity Bus Transceivers
Ciclo vital:
Nuevo de este fabricante.
Ficha de datos:
SN74ABT853DBRE4 Ficha de datos
Entrega:
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ECAD Model:
Más información:
SN74ABT853DBRE4 más información SN74ABT853DBRE4 Product Details
Atributo del producto
Valor de atributo
Fabricante:
Instrumentos Texas
Categoria de producto:
Transceptores de bus
RoHS:
Y
Familia lógica:
74ABT
Nivel de entrada:
TTL
Nivel de salida:
TTL
Tipo de salida:
3-State
Corriente de salida de alto nivel:
- 32 mA
Corriente de salida de nivel bajo:
64 mA
Tiempo de retardo de propagación:
4.8 ns
Voltaje de suministro - Máx:
5.5 V
Voltaje de suministro - Min:
4.5 V
Temperatura mínima de funcionamiento:
- 40 C
Temperatura máxima de funcionamiento:
+ 85 C
Paquete / Caja:
SSOP-24
Embalaje:
Carrete
Función:
Transceptor de bus con verificador de paridad
Altura:
1.95 mm
Longitud:
8.2 mm
Numero de circuitos:
1
Producto:
BiCMOS
Corriente de reposo:
24 mA
Tecnología:
BiCMOS
Ancho:
5.3 mm
Marca:
Instrumentos Texas
Estilo de montaje:
SMD / SMT
Número de canales:
8
Corriente de suministro - Máx .:
38 mA
Voltaje de suministro operativo:
4.5 V to 5.5 V
Polaridad:
No inversor
Tipo de producto:
Transceptores de bus
Cantidad de paquete de fábrica:
1
Subcategoría:
Circuitos integrados lógicos
Unidad de peso:
0.059966 oz
Tags
SN74ABT853DB, SN74ABT853D, SN74ABT853, SN74ABT85, SN74ABT8, SN74AB, SN74A, SN74, SN7
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We guarantee 100% customer satisfaction.

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We provide 90-360 days warranty.

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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC TRANSCVR 8-9BIT INVERT 24SSOP
***as Instruments
The 'ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR\) output indicates whether or not an error in the B data has occurred. The output-enable (OEA\ and OEB\) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT853 transceivers provide true data at their outputs. A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR\ flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE\) and clear (CLR\) control inputs. When both OEA\ and OEB\ are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Disponibilidad
Valores:
Available
En orden:
5000
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