TSB41AB2PAP

Mfr. #:: TSB41AB2PAP
Descripción:: 1394 Interface IC Two-Port Cable Xcvr/Arbiter
Ciclo vital:: Nuevo de este fabricante.
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Atributo del producto
Valor de atributo

Fabricante:: Instrumentos Texas

Categoria de producto:: 1394 Interface IC

RoHS:: Y

Estilo de montaje:: SMD / SMT

Paquete / Caja:: HTQFP-64

Serie:: TSB41AB2

Producto:: IEEE 1394a

Velocidad de datos:: 400 Mb/s

Voltaje de suministro operativo:: 3.3 V

Corriente de suministro de funcionamiento:: 71 mA

Temperatura mínima de funcionamiento:: 0 C

Temperatura máxima de funcionamiento:: + 70 C

Embalaje:: Bandeja

Descripción / Función:: IEEE 1394A TWO-PORT CABLE TRANSCEIVER/ARBITER

Marca:: Instrumentos Texas

Sensible a la humedad:: Yes

Tipo de producto:: 1394 Interface IC

Protocolo admitido:: 1394

Cantidad de paquete de fábrica:: 160

Subcategoría:: Circuitos integrados de interfaz

Unidad de peso:: 0.017506 oz

Tags: TSB41AB2PA, TSB41AB2P, TSB41AB2, TSB41AB, TSB41A, TSB41, TSB4, TSB

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

TSB41AB2PAP Descripción

***asInstruments: IEEE1394a2portcabletransceiverarbiter64HTQFP0to70

***eco: TwoPortCableTransceiverArbiter1TX1Receiver400Mbps64PinHTQFPEP

***ment14APAC: ControllerIC;PackageCase64HTQFP;Da

***ark: IcController400MbpsSmdRohsCompliantYes

***ser: IEEE1394FirewireTwoPortCableXcvrArbiter

***iKey: ICTRANSCEIVERHALF4464HTQFP

***SourceElectronics: ICCABLEXCVRARBITER64HTQFP

***AS INSTRUMEN: The TSB41AB2 provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based IEEE 1394 network. The cable ports incorporate two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB2 is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A.

***AS INSTRU: The TSB41AB2 requires only an external 24.576-MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.

***AS INSTRUMEN: The TSB41AB2 supports an optional isolation barrier between itself and its LLC. When the ISO\ input terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation, the ISO\ terminal on the PHY must be high.

***AS INSTRUMENTS INC: Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41AB2 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s).

***AS INSTRUMENTS INC: During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC.

***: Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage.

***NS: The TSB41AB2 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. TPBIAS is close to VDD when an active port is not connected to another node.

***ASI: The line drivers in the TSB41AB2 operate in a high-impedance current mode, and are designed to work with external 112- ±1.0%.

***NS: When the power supply of the TSB41AB2 is off while the twisted-pair cables are connected, the TSB41AB2 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power plane.

***TEXAS: When the TSB41AB2 is used with one of the ports not brought out to a connector, the twisted-pair terminals of the unused port must be terminated for reliable operation. For each unused port, the TPB+ and TPB terminals should be tied together and then pulled to ground, or the TPB+ and TPB terminals should be connected to the suggested termination network (see Figure 5). The TPA+ and TPA and TPBIAS terminals of an unused port may be left unconnected. The TPBIAS terminal should be connected to a 1-µF capacitor to ground or left floating.

***: The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDD through a 1-k resistor, and SM should be connected directly to ground.

***: Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are tied high through a 1-k resistor or hardwired low as a function of the equipment design. The PC0PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM).

***TEXAS: The TSB41AB2 supports suspend/resume as defined in IEEE 1394a-2000 specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low-power state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBIAS. When ports of the TSB41AB2 are suspended, all circuits except the band gap reference generator and bias detection circuits are powered down, resulting in significant power savings. For additional details of suspend/resume operation see IEEE 1394a-2000. The use of suspend/resume is recommended for new designs.

***XS: The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET\ input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBIAS output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC.

***AS INSTUMENTS: The cable-not-active (CNA) output terminal is asserted high when there are no twisted-pair cable ports receiving incoming bias (that is, they are either disconnected or suspended), and can be used along with LPS to determine when to power down the TSB41AB2. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET\ terminal to force a reset of the TSB41AB2 internal logic.

***INS: The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the Application Information section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit).

***TEXAS: The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41AB2 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41AB2 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it to normal operation.

***AS INSTRUMENTS INCORPORATED: When the PHY-LLC interface is in the low-power disabled state, the TSB41AB2 automatically enters a low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41AB2 disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the port (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt enable bit cleared. The TSB41AB2 exits the low-power mode when the LPS input is asserted high or when a port event occurs. This requires that the TSB41AB2 become active in order to respond to the event or to notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes active (and the PHY-LLC interface is initialized and become operative) within 7.3 ms after LPS is asserted high when the TSB41AB2 is in the low-power mode.

***AS INSTRU: The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON to be active.

Market price

Parte #	Descripción	Valores	Precio
TSB41AB2PAP DISTI # V39:1801_07426985	Two Port Cable Transceiver/Arbiter 1TX 1RX 400Mbps 64-Pin HTQFP EP Tray RoHS: Compliant	174	24000:$3.2090 8000:$3.2120 4000:$3.2150 160:$4.0590
TSB41AB2PAPG4 DISTI # V39:1801_07426986	TRANSCEIVER/ARBITER RoHS: Compliant	17	24000:$4.4240 8000:$4.6390 4000:$4.9740 160:$5.4640
TSB41AB2PAP DISTI # 296-11076-ND	IC CABLE XCVR/ARBITER 64-HTQFP RoHS: Compliant Min Qty: 1 Container: Tray	2296In Stock	2560:$3.3176 1120:$3.4452 640:$3.9556 160:$4.5426 25:$5.2316 10:$5.4870 1:$6.0700
TSB41AB2PAPR DISTI # 296-44340-1-ND	IC CABLE XCVR/ARBITER 64-HTQFP RoHS: Compliant Min Qty: 1 Container: Cut Tape (CT)	807In Stock	500:$3.7171 100:$4.3665 10:$5.3290 1:$5.9300
TSB41AB2PAPR DISTI # 296-44340-6-ND	IC CABLE XCVR/ARBITER 64-HTQFP RoHS: Compliant Min Qty: 1 Container: Digi-Reel®	807In Stock	500:$3.7171 100:$4.3665 10:$5.3290 1:$5.9300
TSB41AB2PAPR DISTI # 296-44340-2-ND	IC CABLE XCVR/ARBITER 64-HTQFP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Temporarily Out of Stock	2000:$2.8914 1000:$3.0436
TSB41AB2PAPRG4 DISTI # TSB41AB2PAPRG4-ND	IC CABLE XCVR/ARBITER 64-HTQFP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Temporarily Out of Stock	1000:$3.0436
TSB41AB2PAPG4 DISTI # TSB41AB2PAPG4-ND	IC CABLE XCVR/ARBITER 64-HTQFP RoHS: Compliant Min Qty: 160 Container: Tray	Temporarily Out of Stock	160:$4.5426
TSB41AB2PAP DISTI # 25734289	Two Port Cable Transceiver/Arbiter 1TX 1RX 400Mbps 64-Pin HTQFP EP Tray RoHS: Compliant	160	160:$4.0590
TSB41AB2PAPG4 DISTI # 25734290	TRANSCEIVER/ARBITER RoHS: Compliant	17	17:$5.4640
TSB41AB2PAP DISTI # TSB41AB2PAP	Two port Cable Transceiver And Arbiter 64-Pin HTQFP EP Tray (Alt: TSB41AB2PAP) RoHS: Compliant Min Qty: 1 Container: Tray	Europe - 20	1:€5.9100 10:€4.8200 25:€4.4600 50:€4.2300 100:€3.9900 250:€3.7900 500:€3.0300
TSB41AB2PAP DISTI # TSB41AB2PAP	Two port Cable Transceiver And Arbiter 64-Pin HTQFP EP Tray - Trays (Alt: TSB41AB2PAP) RoHS: Compliant Min Qty: 1 Container: Tray	Americas - 0	1:$3.4900 10:$3.4900 25:$3.4900 50:$3.4900 100:$3.4900 500:$3.1900 1000:$3.0900
TSB41AB2PAPR DISTI # TSB41AB2PAPR	Two port Cable Transceiver And Arbiter 64-Pin HTQFP EP T/R - Tape and Reel (Alt: TSB41AB2PAPR) RoHS: Compliant Min Qty: 1000 Container: Reel	Americas - 0	1000:$3.0900 2000:$2.9900 4000:$2.8900 6000:$2.7900 10000:$2.6900
TSB41AB2PAPR DISTI # TSB41AB2PAPR	Two port Cable Transceiver And Arbiter 64-Pin HTQFP EP T/R (Alt: TSB41AB2PAPR) RoHS: Compliant Min Qty: 1000 Container: Tape and Reel	Europe - 0	1000:€3.5900 2000:€3.1900 4000:€2.7900 6000:€2.6900 10000:€2.5900
TSB41AB2PAPG4 DISTI # TSB41AB2PAPG4	Two port Cable Transceiver And Arbiter 64-Pin HTQFP EP Tray - Rail/Tube (Alt: TSB41AB2PAPG4) RoHS: Compliant Min Qty: 160 Container: Tube	Americas - 0	160:$3.6900 320:$3.4900 640:$3.3900 960:$3.1900 1600:$3.1900
TSB41AB2PAPG4 DISTI # TSB41AB2PAPG4	Two port Cable Transceiver And Arbiter 64-Pin HTQFP EP Tray (Alt: TSB41AB2PAPG4) RoHS: Compliant Min Qty: 1 Container: Tray	Europe - 0	1:€4.1900 10:€3.9900 25:€3.6900 50:€3.4900 100:€3.2900 500:€3.1900 1000:€2.9900
TSB41AB2PAPRG4 DISTI # TSB41AB2PAPRG4	Two port Cable Transceiver And Arbiter 64-Pin HTQFP EP T/R - Tape and Reel (Alt: TSB41AB2PAPRG4) RoHS: Compliant Min Qty: 1000 Container: Reel	Americas - 0	1000:$3.0900 2000:$2.9900 4000:$2.8900 6000:$2.7900 10000:$2.6900
TSB41AB2PAP DISTI # 62M0808	IC, CONTROLLER, 400MBPS, SMD,Device Type:Cable Transceiver,Data Rate:400Mbps,Supply Voltage Min:3V,Supply Voltage Max:3.6V,Driver Case Style:HTQFP,No. of Pins:64,Operating Temperature Min:0°C,Operating Temperature Max:70°C,, RoHS Compliant: Yes	234	1:$6.0700 10:$5.4900 25:$5.0800 50:$4.8200 100:$4.5500 250:$4.3200 500:$3.9600
TSB41AB2PAP DISTI # 77C1439	CABLE TRANSCEIVER/ARBITER, 400MBPS, HTQFP64,Device Type:Cable Transceiver,Data Rate:400Mbps,Supply Voltage Min:3V,Supply Voltage Max:3.6V,Driver Case Style:HTQFP,No. of Pins:64Pins,Operating Temperature Min:0°C,Packaging:Each, RoHS Compliant: Yes	163	1:$6.0700 10:$5.4900 25:$5.0800 50:$4.8200 100:$4.5500 250:$4.3200 500:$3.9600
TSB41AB2PAP	IEEE 1394a Two-Port Cable Transceiver/Arbiter	6350	1000:$2.9000 750:$2.9600 500:$3.4200 250:$3.9300 100:$4.2100 25:$4.7000 10:$5.0300 1:$5.5900
TSB41AB2PAPR	IEEE 1394a Two-Port Cable Transceiver/Arbiter	4000	1000:$2.4700 750:$2.5900 500:$3.0700 250:$3.6100 100:$3.8500 25:$4.3900 10:$4.7200 1:$5.2400
TSB41AB2PAP	Line Transceiver, 4 Func, 4 Driver, 4 Rcvr, CMOS, PQFP64 RoHS: Compliant	92225	1000:$3.7700 500:$3.9600 100:$4.1300 25:$4.3000 1:$4.6300
TSB41AB2PAPR	Line Transceiver, 4 Func, 4 Driver, 4 Rcvr, PQFP64 RoHS: Compliant	2749	1000:$3.2100 500:$3.3800 100:$3.5100 25:$3.6600 1:$3.9500
TSB41AB2PAPG4	Line Transceiver, 4 Func, 4 Driver, 4 Rcvr, CMOS, PQFP64 RoHS: Compliant	110	1000:$3.7700 500:$3.9600 100:$4.1300 25:$4.3000 1:$4.6300
TSB41AB2PAPR DISTI # 595-TSB41AB2PAPR	1394 Interface IC Two-Port Cable Xcvr/Arbiter RoHS: Compliant	1556	1:$5.7600 10:$5.1700 100:$4.2400 250:$3.9700 500:$3.6000 1000:$3.0400 2000:$2.8900
TSB41AB2PAP DISTI # 595-TSB41AB2PAP	1394 Interface IC Two-Port Cable Xcvr/Arbiter RoHS: Compliant	268	1:$6.0700 10:$5.4900 25:$5.0800 100:$4.5500 250:$4.3200 500:$3.9600 1000:$3.4500
TSB41AB2PAPG4 DISTI # 595-TSB41AB2PAPG4	1394 Interface IC Two-Port Cable Xcvr/Arbiter RoHS: Compliant	0	160:$4.5500 320:$4.3200 640:$3.9600 1120:$3.4500
TSB41AB2PAPRG4 DISTI # 595-TSB41AB2PAPRG4	1394 Interface IC IEEE1394a 2Port Cable Xcvr/Arbiter RoHS: Compliant	0	1000:$3.0400 2000:$2.8900
TSB41AB2PAP DISTI # 5458410P	LINE DRIVER TSB41AB2PAP, PU	185	8:£4.0600 40:£3.7100 80:£3.5500
TSB41AB2PAP DISTI # 5458410	LINE DRIVER TSB41AB2PAP, EA	105	1:£4.7300 8:£4.0600 40:£3.7100 80:£3.5500
TSB41AB2PAP	Line Transceiver, 4-Driver, 4-Receiver, 64 Pin, Plastic, TQFP	92	93:$1.8850 10:$2.1750 1:$4.3500
TSB41AB2PAP	Line Transceiver, 4-Driver, 4-Receiver, 64 Pin, Plastic, TQFP	20	11:$6.9400 4:$7.6340 1:$10.4100
TSB41AB2PAPG4	Line Transceiver, 4-Driver, 4-Receiver, 64 Pin, Plastic, TQFP	26	6:$4.1250 2:$5.5000 1:$8.2500
TSB41AB2PAP		441
TSB41AB2PAPG4		4
TSB41AB2PAP	INSTOCK	10145
TSB41AB2PAP DISTI # 1470524	IC, CONTROLLER, 400MBPS, SMD RoHS: Compliant	397	1:£5.0700 10:£4.1600 25:£3.8400 50:£3.6400 100:£3.4400
TSB41AB2PAP DISTI # C1S746201623700	Two Port Cable Transceiver/Arbiter 1TX 1RX 400Mbps 64-Pin HTQFP EP Tray RoHS: Compliant	174	160:$4.6160
TSB41AB2PAP DISTI # 1470524	IC, CONTROLLER, 400MBPS, SMD RoHS: Compliant	418	1:$9.6100 10:$8.6900 25:$8.0500 100:$7.2100 250:$6.8400 500:$6.2700 1000:$5.4600 2500:$5.2500

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TSB41AB2PAP

Step1:Vacuum Packaging with PL

Step2:Anti-Static Bag

Step3:Packaging Boxes

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes