CDC857-3DGGG4

CDC857-3DGGG4
Mfr. #:
CDC857-3DGGG4
Descripción:
IC 3.3V PLL CLK-DRVR 48-TSSOP
Ciclo vital:
Nuevo de este fabricante.
Ficha de datos:
CDC857-3DGGG4 Ficha de datos
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Más información:
CDC857-3DGGG4 más información CDC857-3DGGG4 Product Details
Atributo del producto
Valor de atributo
Tags
CDC857-3, CDC85, CDC8, CDC
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC 3.3V PLL CLK-DRVR 48-TSSOP
***ark
IC, PLL CLOCK DRIVER, 167MHZ, TSSOP-48; Clock IC Type:PLL Clock Driver; Frequency:167MHz; No. of Outputs:10; Supply Current:235mA; Supply Voltage Range:3V to 3.6V; Digital IC Case Style:TSSOP; No. of Pins:48 ;RoHS Compliant: Yes
***as Instruments
The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer). The CDC857-2 operates at 2.5 V (PLL and output buffer). One bank of ten inverting and noninverting outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance state (3-state). Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. If AVCC is at GND and VCC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being disabled, after AVCC ramps up to its specified VCC value, with G being kept low. The CDC857 is characterized for operation from 0C to 85C.
Parte # Descripción Valores Precio
CDC857-3DGGG4
DISTI # CDC857-3DGGG4-ND
IC 3.3V PLL CLK-DRVR 48-TSSOP
RoHS: Compliant
Min Qty: 80
Container: Tube
Limited Supply - Call
    CDC857-3DGGG4
    DISTI # 595-CDC857-3DGGG4
    Phase Locked Loops - PLL Phase-Lock Loop Clock Drivers
    RoHS: Compliant
    0
      Imagen Parte # Descripción
      CDC857-3DGGG4

      Mfr.#: CDC857-3DGGG4

      OMO.#: OMO-CDC857-3DGGG4

      Phase Locked Loops - PLL Phase-Lock Loop Clock Drivers
      CDC857-2DGGRG4

      Mfr.#: CDC857-2DGGRG4

      OMO.#: OMO-CDC857-2DGGRG4

      Clock Drivers & Distribution Phase-Lock Loop Clock Drivers
      CDC857-2DGG

      Mfr.#: CDC857-2DGG

      OMO.#: OMO-CDC857-2DGG

      Clock Drivers & Distribution Phase-Lock Loop Clock Drivers
      CDC857-2

      Mfr.#: CDC857-2

      OMO.#: OMO-CDC857-2-1190

      Nuevo y original
      CDC857-20GGR

      Mfr.#: CDC857-20GGR

      OMO.#: OMO-CDC857-20GGR-1190

      Nuevo y original
      CDC857-2DGGRD4

      Mfr.#: CDC857-2DGGRD4

      OMO.#: OMO-CDC857-2DGGRD4-1190

      Nuevo y original
      CDC857-3DGG

      Mfr.#: CDC857-3DGG

      OMO.#: OMO-CDC857-3DGG-TEXAS-INSTRUMENTS

      IC 3.3V PLL CLK-DRVR 48-TSSOP
      CDC8573DGGR

      Mfr.#: CDC8573DGGR

      OMO.#: OMO-CDC8573DGGR-1190

      Nuevo y original
      CDC857B

      Mfr.#: CDC857B

      OMO.#: OMO-CDC857B-1190

      Nuevo y original
      CDC857-3DGGG4

      Mfr.#: CDC857-3DGGG4

      OMO.#: OMO-CDC857-3DGGG4-TEXAS-INSTRUMENTS

      IC 3.3V PLL CLK-DRVR 48-TSSOP
      Disponibilidad
      Valores:
      Available
      En orden:
      3000
      Ingrese la cantidad:
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