SN74LVC823ANSR

SN74LVC823ANSR
Mfr. #:
SN74LVC823ANSR
Descripción:
Flip Flops 9-Bit Bus Intfc FlipFlop W/3-St Otpt
Ciclo vital:
Nuevo de este fabricante.
Ficha de datos:
SN74LVC823ANSR Ficha de datos
Entrega:
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ECAD Model:
Más información:
SN74LVC823ANSR más información SN74LVC823ANSR Product Details
Atributo del producto
Valor de atributo
Fabricante:
Instrumentos Texas
Categoria de producto:
Chancletas
RoHS:
Y
Numero de circuitos:
1
Familia lógica:
74LV
Tipo de lógica:
Flip-Flop de interfaz de bus
Polaridad:
No inversor
Tipo de entrada:
De un solo extremo
Tipo de salida:
De un solo extremo
Tiempo de retardo de propagación:
8.9 ns
Corriente de salida de alto nivel:
- 24 mA
Corriente de salida de nivel bajo:
24 mA
Voltaje de suministro - Min:
1.65 V
Voltaje de suministro - Máx:
3.6 V
Temperatura mínima de funcionamiento:
- 40 C
Temperatura máxima de funcionamiento:
+ 85 C
Estilo de montaje:
SMD / SMT
Paquete / Caja:
SO-24
Embalaje:
Carrete
Función:
Interfaz de bus tipo D
Altura:
1.95 mm
Longitud:
15 mm
Corriente de reposo:
10 uA
Ancho:
5.3 mm
Marca:
Instrumentos Texas
Número de canales:
9
Número de líneas de entrada:
9
Número de líneas de salida:
3
Voltaje de suministro operativo:
1.65 V to 3.6 V
Tipo de producto:
Chancletas
Tipo de reinicio:
Reinicio maestro
Cantidad de paquete de fábrica:
1
Subcategoría:
Circuitos integrados lógicos
Unidad de peso:
0.010857 oz
Tags
SN74LVC823, SN74LVC82, SN74LVC8, SN74LVC, SN74LV, SN74L, SN74, SN7
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We provide 90-360 days warranty.

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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Bus Driver, LVC/LCX/Z Series, 1-Func, 9-Bit, True Output, CMOS, PDSO24
***i-Key
IC D-TYPE POS TRG SNGL 24SO
***el Nordic
Contact for details
***as Instruments
This 9-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC823A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. With the clock-enable (CLKEN)\ input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR)\ input low causes the nine Q outputs to go low, independently of the clock. A buffered output-enable (OE)\ input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or the high-impedance state. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Available
En orden:
3500
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