TSB43AB22APDT

TSB43AB22APDT
Mfr. #:
TSB43AB22APDT
Descripción:
1394 Interface IC OHCI 1.1 1394a Link Layer Cntrlr Intgrt
Ciclo vital:
Nuevo de este fabricante.
Ficha de datos:
TSB43AB22APDT Ficha de datos
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Más información:
TSB43AB22APDT más información TSB43AB22APDT Product Details
Atributo del producto
Valor de atributo
Fabricante:
Instrumentos Texas
Categoria de producto:
1394 Interface IC
RoHS:
Y
Estilo de montaje:
SMD / SMT
Paquete / Caja:
TQFP-128
Serie:
TSB43AB22A
Producto:
IEEE 1394a
Escribe:
OHCI Lynx Controller
Velocidad de datos:
400 Mb/s
Voltaje de suministro operativo:
3.3 V
Corriente de suministro de funcionamiento:
20 mA
Temperatura mínima de funcionamiento:
0 C
Temperatura máxima de funcionamiento:
+ 70 C
Embalaje:
Bandeja
Descripción / Función:
OHCI 1.1, 1394A LINK LAYER CONTROLLER INTEGRATED WITH 1394A, 400MBPS, 2-PORT PHYSICAL LAYER (PHY)
Marca:
Instrumentos Texas
Sensible a la humedad:
Yes
Tipo de producto:
1394 Interface IC
Protocolo admitido:
1394
Cantidad de paquete de fábrica:
90
Subcategoría:
Circuitos integrados de interfaz
Unidad de peso:
0.017760 oz
Tags
TSB43AB22APDT, TSB43AB22AP, TSB43AB22A, TSB43AB22, TSB43AB2, TSB43AB, TSB43A, TSB43, TSB4, TSB
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***ical
Integrated 1394a-2000 OHCI PHY/Link-Layer Controller Serial Interface 3.3V 128-Pin TQFP Tray
***as Instruments
OHCI 1.1, 1394a link layer controller with integrated IEEE 1394a, 400-Mbps, 2-port PHY 128-TQFP 0 to 70
***ser
IEEE1394 (Firewire) OHCI 1.1, 1394a Link Layer Cntrlr Intgrt
*** Source Electronics
IC 1394A LINK LYR CNTLR 128-TQFP
***i-Key
IC CONTROLLER LINK LAYER 128TQFP
***S
French Electronic Distributor since 1988
***eco
IEEE-1394.A 400MBPS 2 PORT LINK-PHY INT
***i-Key Marketplace
TSB43AB22A OHCI 1.1, 1394A LINK
***ment14 APAC
IC, 1394A LINK LYR CNTLR 128-TQFP; Device Type:Link Layer Controller; Data Rate:400Mbps; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Driver Case Style:TQFP; No. of Pins:128Pins; Operating Temperature Min:0°C; Operating Temperature Max:70°C; Product Range:-; MSL:MSL 3 - 168 hours; SVHC:No SVHC (15-Jan-2019); Base Number:43; Operating Temperature Range:0°C to +70°C; Supply Current:92.4mA; Supply Voltage Range:3V to 3.6V; Termination Type:Surface Mount Device
***
The Texas Instruments TSB43AB22A device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB22A device provides two 1394 ports that have separate cable bias (TPBIAS). The TSB43AB22A device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.
***AS INSTRUMENTS INCORPORATED
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the TSB43AB22A device is compliant with the PCI Bus Power Management Interface Specification as specified by the PC 2001 Design Guide requirements. The TSB43AB22A device supports the D0, D1, D2, and D3 power states.
***as Instruments Inc.
The TSB43AB22A design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the 1394 data.
***AS INS
The TSB43AB22A device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB43AB22A device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers.
***AS INSTR
An advanced CMOS process achieves low power consumption and allows the TSB43AB22A device to operate at PCI clock rates up to 33 MHz.
***as Instruments Inc.
The TSB43AB22A PHY-layer provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission.
***AS INSTRUMEN
The TSB43AB22A PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data.
***AS
Data bits to be transmitted through the cable ports are received from the integrated LLC and are latched internally in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the twisted-pair B (TPB) cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair A (TPA) cable pair(s).
***AS INSTRUMENT
During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are resynchronized to the local 49.152-MHz system clock and sent to the integrated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports.
***AS INSTRUMENT
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage.
***as Instruments Inc.
The TSB43AB22A device provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY layer contains two independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1.0 uF.
***TEXAS
The line drivers in the TSB43AB22A device operate in a high-impedance current mode and are designed to work with external 112- cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56- resistors. The midpoint of the pair of resistors that is directly connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to ground through a parallel R-C network with recommended values of 5 k and 220 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current and other internal operating currents. This current-setting resistor has a value of 6.34 k ±1%.
***AS INSTUMENTS
When the power supply of the TSB43AB22A device is off and the twisted-pair cables are connected, the TSB43AB22A transmitter and receiver circuitry present a high impedance to the cable and do not load the TPBIAS voltage at the other end of the cable.
***AS INSTRUMENTS INC
When the device is in a low-power state (for example, D2 or D3) the TSB43AB22A device automatically enters a low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB43AB22A device disables its internal clock generators and also disables various voltage and current reference circuits, depending on the state of the ports (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power sleep mode) is attained when all ports are either disconnected or disabled with the port interrupt enable bit cleared.
***AS INSTRUMEN
The TSB43AB22A device exits the low-power mode when bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1 or when a port event occurs which requires that the TSB43AB22A device to become active in order to respond to the event or to notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, or a new connection is detected on a nondisabled port). When the TSB43AB22A device is in the low-power mode, the internal 49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within 2 ms after bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1.
***as Instr.
The TSB43AB22A device supports hardware enhancements to better support digital video (DV) and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous receive digital video enhancements register at OHCI offset A88h (see Chapter 5, TI Extension Registers). The enhancements include automatic timestamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for received DV streams.
***AS INSTRU
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data contexts are implemented as hardware support for the synchronization timestamp for both DV and MPEG CIP formats. The TSB43AB22A device supports modification of the synchronization timestamp field to ensure that the value inserted via software is not stale–that is, the value is less than the current cycle timer when the packet is transmitted.
Parte # Descripción Valores Precio
TSB43AB22APDT
DISTI # V39:1801_07427015
Integrated 1394a-2000 OHCI PHY/Link-Layer Controller 3.3V 128-Pin TQFP Tray
RoHS: Compliant
32
  • 45000:$4.9550
  • 18000:$5.0020
  • 9000:$5.0070
  • 90:$6.9190
TSB43AB22APDT
DISTI # 296-12569-ND
IC CONTROLLER LINK LAYER 128TQFP
RoHS: Compliant
Min Qty: 1
Container: Tray
3402In Stock
  • 1080:$5.1921
  • 540:$5.9613
  • 180:$6.8459
  • 90:$7.8843
  • 10:$8.2690
  • 1:$9.1500
STSB43AB22APDTG4
DISTI # STSB43AB22APDTG4-ND
IC PHY/LINK LAYER CTRLR 128-TQFP
RoHS: Compliant
Min Qty: 90
Container: Tube
Limited Supply - Call
    TSB43AB22APDTG4
    DISTI # TSB43AB22APDTG4-ND
    IC CONTROLLER LINK LAYER 128TQFP
    RoHS: Compliant
    Min Qty: 90
    Container: Tube
    Temporarily Out of Stock
    • 90:$7.8843
    TSB43AB22APDT
    DISTI # 25734298
    Integrated 1394a-2000 OHCI PHY/Link-Layer Controller 3.3V 128-Pin TQFP Tray
    RoHS: Compliant
    32
    • 32:$6.9190
    TSB43AB22APDT
    DISTI # TSB43AB22APDT
    OHCI PHY/Link Layer Controller 128-Pin TQFP Tray - Trays (Alt: TSB43AB22APDT)
    RoHS: Compliant
    Min Qty: 90
    Container: Tray
    Americas - 0
    • 90:$6.3900
    • 180:$6.1900
    • 360:$5.9900
    • 540:$5.7900
    • 900:$5.6900
    TSB43AB22APDT
    DISTI # TSB43AB22APDT
    OHCI PHY/Link Layer Controller 128-Pin TQFP Tray (Alt: TSB43AB22APDT)
    RoHS: Compliant
    Min Qty: 1
    Container: Tray
    Europe - 0
    • 1:€6.9500
    • 10:€5.0500
    • 100:€4.5400
    • 250:€4.2700
    • 500:€3.9200
    TSB43AB22APDTG4
    DISTI # TSB43AB22APDTG4
    OHCI PHY/Link Layer Controller 128-Pin TQFP Tray - Rail/Tube (Alt: TSB43AB22APDTG4)
    RoHS: Compliant
    Min Qty: 90
    Container: Tube
    Americas - 0
    • 90:$5.4900
    • 180:$5.2900
    • 360:$5.0900
    • 540:$4.8900
    • 900:$4.7900
    TSB43AB22APDTG4
    DISTI # TSB43AB22APDTG4
    OHCI PHY/Link Layer Controller 128-Pin TQFP Tray (Alt: TSB43AB22APDTG4)
    RoHS: Compliant
    Min Qty: 1
    Container: Tray
    Europe - 0
    • 1:€6.3900
    • 10:€5.9900
    • 25:€5.6900
    • 50:€5.3900
    • 100:€5.0900
    • 500:€4.7900
    • 1000:€4.5900
    TSB43AB22APDTOHCI 1.1, 1394a Link Layer Controller integrated with 1394a, 400Mbps, 2-port Physical Layer (PHY)6300
    • 1000:$4.3700
    • 750:$4.4600
    • 500:$5.1500
    • 250:$5.9200
    • 100:$6.3500
    • 25:$7.0800
    • 10:$7.5800
    • 1:$8.4200
    TSB43AB22APDTSerial I/O Controller, 1 Channel(s), 50MBps, CMOS, PQFP128
    RoHS: Compliant
    77351
    • 1000:$5.6600
    • 500:$5.9600
    • 100:$6.2100
    • 25:$6.4700
    • 1:$6.9700
    TSB43AB22APDTG4Serial I/O Controller, 1 Channel(s), 50MBps, CMOS, PQFP128
    RoHS: Compliant
    52920
    • 1000:$5.6600
    • 500:$5.9600
    • 100:$6.2100
    • 25:$6.4700
    • 1:$6.9700
    TSB43AB22APDT
    DISTI # 595-TSB43AB22APDT
    1394 Interface IC OHCI 1.1 1394a Link Layer Cntrlr Intgrt
    RoHS: Compliant
    184
    • 1:$9.1500
    • 10:$8.2700
    • 25:$7.6600
    • 100:$6.8500
    • 250:$6.5000
    • 500:$5.9700
    • 1000:$5.2000
    TSB43AB22APDTG4
    DISTI # 595-TSB43AB22APDTG4
    1394 Interface IC OHCI 1.1 1394a Link Layer Cntrlr Intgrt
    RoHS: Compliant
    0
    • 90:$7.6600
    • 180:$6.8500
    • 270:$6.5000
    • 540:$5.9700
    • 1080:$5.2000
    STSB43AB22APDTG4
    DISTI # 595-STSB43AB22APDTG4
    1394 Interface IC OHCI 1.1 1394a Link Layer Controller
    RoHS: Compliant
    0
      TSB43AB22APDTG41 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP128 (Also Known As: TSB43AB22APDT)6
      • 5:$4.5000
      • 2:$6.0000
      • 1:$9.0000
      TSB43AB22APDTG41 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP1286
      • 5:$4.5000
      • 2:$6.0000
      • 1:$9.0000
      TSB43AB22APDT
      DISTI # 6625232P
      INTEGRATED OHCI PHY/LINK-LAYER, PU63
      • 5:£6.3300
      • 10:£6.0200
      TSB43AB22APDT
      DISTI # 1755451
      IC, 1394A LINK LYR CNTLR 128-TQFP
      RoHS: Not Compliant
      15
      • 1:$12.7700
      TSB43AB22APDT
      DISTI # 1755451
      IC, 1394A LINK LYR CNTLR 128-TQFP
      RoHS: Not Compliant
      6
      • 1:£7.4800
      • 10:£6.2600
      • 25:£5.7900
      • 50:£5.4900
      • 100:£5.1800
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      Disponibilidad
      Valores:
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      En orden:
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      Ingrese la cantidad:
      El precio actual de TSB43AB22APDT es solo de referencia, si desea obtener el mejor precio, envíe una consulta o envíe un correo electrónico directo a nuestro equipo de ventas [email protected]
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