OMO ElectronicOMO Electronic
Expand menu
Hola, regístrateMi cuenta
0 Carro

TSB41LV06APZP

TSB41LV06APZP
Mfr. #:
TSB41LV06APZP
Descripción:
1394 Interface IC Six-Port Cable Xcvr/Arbiter
Ciclo vital:
Nuevo de este fabricante.
Ficha de datos:
TSB41LV06APZP Ficha de datos
Entrega:
DHL FedEx Ups TNT EMS
Pago:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
Más información:
TSB41LV06APZP más información TSB41LV06APZP Product Details
Atributo del producto
Valor de atributo
Fabricante:
Instrumentos Texas
Categoria de producto:
1394 Interface IC
RoHS:
Y
Estilo de montaje:
SMD / SMT
Paquete / Caja:
HTQFP-100
Serie:
TSB41LV06A
Producto:
IEEE 1394a
Velocidad de datos:
400 Mb/s
Voltaje de suministro operativo:
3.3 V
Corriente de suministro de funcionamiento:
280 mA
Temperatura mínima de funcionamiento:
0 C
Temperatura máxima de funcionamiento:
+ 70 C
Embalaje:
Bandeja
Descripción / Función:
IEEE 1394A SIX-PORT CABLE TRANSCEIVER/ARBITER
Marca:
Instrumentos Texas
Sensible a la humedad:
Yes
Tipo de producto:
1394 Interface IC
Protocolo admitido:
1394
Cantidad de paquete de fábrica:
90
Subcategoría:
Circuitos integrados de interfaz
Unidad de peso:
0.017827 oz
Tags
TSB41LV06AP, TSB41LV06A, TSB41LV06, TSB41LV0, TSB41L, TSB41, TSB4, TSB
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***as Instruments
IEEE 1394a 6-port cable transceiver/arbiter 100-HTQFP 0 to 70
***ical
Cable Transceiver/Arbiter 1TX 1RX 400Mbps 100-Pin HTQFP EP Tray
***C
Twelve Transmitter/Receiver IEEE-1394a 100-Pin HTQFP EP Twelve Transmitter/Receiver IEEE-1394a 100-Pin HTQFP EP
*** Stop Electro
Line Transceiver, 12 Func, 12 Driver, 12 Rcvr, PQFP100
***ark
IC, CABLE TXRX/ARBITER, 400MBPS HTQFP100
***ser
IEEE1394 (Firewire) Six-Port Cable Xcvr/Arbiter
***i-Key
IC TRANSCEIVER HALF 2/2 100HTQFP
***DA Technology Co., Ltd.
Product Description Demo for Development.
*** Source Electronics
IC CABLE XCVR/ARBITER 100-HTQFP
***S
French Electronic Distributor since 1988
***i-Key Marketplace
TSB41LV06A IEEE 1394A SIX-PORT C
***
The TSB41LV06A provides the digital and analog transceiver functions needed to implement a six-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41LV06A is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A.
***as Instr.
The TSB41LV06A requires only an external 24.576 MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.
***as Instruments Inc.
The TSB41LV06A supports an optional isolation barrier between itself and its LLC. When the ISO\ input terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the P1394a Supplement (section 5.9.4) (hereafter referred to as Annex J type isolation). To operate with TI bus holder isolation the ISO\ terminal on the PHY must be high.
***ASIN
Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41LV06A in synchronization with the 49.152 MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s).
***AS INSTRUM
During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two, four, or eight bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports.
***AS INSTRUMENTS INCORPORATED
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage.
***as Instr.
The TSB41LV06A provides a 1.86 V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains six independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 uF.
***AS INSTRUMENT
The line drivers in the TSB41LV06A operate in a high-impedance current mode, and are designed to work with external 112- line-termination resistor networks in order to match the 110- cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56- resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 k and 220 pF. The values of the external line termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.3-k ±1%. This may be accomplished by placing a 6.34-k ±1% resistor in parallel with a 1-M resistor.
***
When the power supply of the TSB41LV06A is off while the twisted-pair cables are connected, the TSB41LV06A transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable.
***NS
When the TSB41LV06A is used with one or more of the ports not brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB- terminals should be tied together and then pulled to ground, or the TPB+ and TPB- terminals should be connected to the suggested termination network. The TPA+ and TPA- and TPBIAS terminals of an unused port may be left unconnected. The TPBIAS terminal may be connected to a 1 uF capacitor to ground or left floating.
***AS INSTRUMENTS INCORPORATED
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDD, SE should be tied to ground through a 1-k resistor, while SM should be connected directly to ground.
***ASI
Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are hardwired high or low as a function of the equipment design. The PC0-PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 1 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM).
***OMO Electronic
The TSB41LV06A supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low power conservation state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBias. When all six ports of the TSB41LV06A are suspended, all circuits except the bandgap reference generator and bias detection circuits are powered down resulting in significant power savings. For additional details of suspend/resume operation refer to the P1394a specification. The use of suspend/resume is recommended for new designs.
***AS INSTR
The port transmitter and receiver circuitry is disabled during power-down (when the PD input terminal is asserted high), during reset (when the RESET\ input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC.
***AS INS
The CNA (cable-not-active) output terminal is asserted high when there are no twisted-pair cable ports receiving incoming bias (i.e., they are either disconnected or suspended), and can be used along with LPS to determine when to power down the TSB41LV06A. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET\ terminal so as to force a reset of the TSB41LV06A internal logic.
***
The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit).
***AS INSTRUM
The LPS input is considered inactive if it remains low for more than 2.6 us and is considered active otherwise. When the TSB41LV06A detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 us, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41LV06A continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and return it to normal operation.
***AS INSRUMENT
When the PHY-LLC interface is in the low-power disabled state, the TSB41LV06A automatically enters a low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41LV06A disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the ports (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the ultralow-power sleep mode) is attained when all ports are either disconnected, or disabled with the port's interrupt enable bit cleared. The TSB41LV06A exits the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41LV06A become active in order to respond to the event or to notify the LLC of the event (e.g., incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes active (and the PHY-LLC interface initializes and becomes operative) within 7.3 ms after LPS is asserted high when the TSB41LV06A is in the low-power mode.
***AS INSTRUMENTS INCORPORATED
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163 ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON to be active.
Parte # Descripción Valores Precio
TSB41LV06APZP
DISTI # 26980731		Cable Transceiver/Arbiter 1TX 1RX 400Mbps 100-Pin HTQFP EP Tray
RoHS: Compliant		30
  • 30:$10.6340
TSB41LV06APZP
DISTI # 296-11079-ND		IC CABLE XCVR/ARBITER 100-HTQFP
RoHS: Compliant
Min Qty: 1
Container: Tray		3111In Stock
  • 540:$11.1607
  • 180:$12.5461
  • 90:$14.2394
  • 10:$14.8550
  • 1:$16.1600
TSB41LV06APZPG4
DISTI # TSB41LV06APZPG4-ND		IC CABLE XCVR/ARBITER 100-HTQFP
RoHS: Compliant
Min Qty: 90
Container: Tube		Temporarily Out of Stock
  • 90:$14.2394
TSB41LV06APZP
DISTI # TSB41LV06APZP		Twelve Transmitter/Receiver IEEE-1394a 100-Pin HTQFP EP Tube - Trays (Alt: TSB41LV06APZP)
RoHS: Compliant
Min Qty: 1
Container: Tray		Americas - 0
  • 1:$13.4900
  • 10:$13.0900
  • 25:$12.7900
  • 50:$12.4900
  • 100:$11.9900
  • 500:$11.6900
  • 1000:$11.4900
TSB41LV06APZP
DISTI # TSB41LV06APZP		Twelve Transmitter/Receiver IEEE-1394a 100-Pin HTQFP EP Tube (Alt: TSB41LV06APZP)
RoHS: Compliant
Min Qty: 1
Container: Tube		Europe - 0
  • 1:€12.1900
  • 10:€11.5900
  • 25:€10.9900
  • 50:€10.4900
  • 100:€9.9900
  • 500:€9.5900
  • 1000:€9.1900
TSB41LV06APZPIEEE 1394a Six-Port Cable Transceiver/Arbiter3600
  • 1000:$8.7500
  • 750:$8.7800
  • 500:$9.7800
  • 250:$10.6200
  • 100:$11.1600
  • 25:$12.7800
  • 10:$13.2400
  • 1:$14.2400
TSB41LV06APZPLine Transceiver, 12 Func, 12 Driver, 12 Rcvr, PQFP100
RoHS: Compliant		126
  • 1000:$11.3200
  • 500:$11.9200
  • 100:$12.4100
  • 25:$12.9400
  • 1:$13.9400
TSB41LV06APZP
DISTI # 595-TSB41LV06APZP		1394 Interface IC Six-Port Cable Xcvr/Arbiter
RoHS: Compliant		88
  • 1:$16.1600
  • 10:$14.8600
  • 25:$14.0900
  • 100:$12.5500
  • 250:$11.9400
  • 500:$11.1700
TSB41LV06APZPG4
DISTI # 595-TSB41LV06APZPG4		1394 Interface IC Six-Port Cable Xcvr/Arbiter
RoHS: Compliant		0
    TSB41LV06APZP
    DISTI # 6625276P    		CABLE TRANSCEIVER 12TR 12TX 12RX 100-PIN, PU114
    • 18:£12.1000
    • 45:£11.6200
    TSB41LV06APZPBUS Controller Circuit, 100 Pin, TQFP93
    • 72:$6.4560
    • 32:$6.9940
    • 1:$10.7600
    Imagen Parte # Descripción
    TSB41LV06APZPG4

    Mfr.#: TSB41LV06APZPG4

    OMO.#: OMO-TSB41LV06APZPG4-TEXAS-INSTRUMENTS

    		 1394 Interface IC Six-Port Cable Xcvr/Arbite
    TSB41LV02A

    Mfr.#: TSB41LV02A

    OMO.#: OMO-TSB41LV02A-1190

    		 Nuevo y original
    TSB41LV03FP

    Mfr.#: TSB41LV03FP

    OMO.#: OMO-TSB41LV03FP-1190

    		 Nuevo y original
    TSB41LV04APFPG4

    Mfr.#: TSB41LV04APFPG4

    OMO.#: OMO-TSB41LV04APFPG4-1190

    		 1394 Interface IC Four-Port Cable Xcvr/Arbite
    TSB41LV06

    Mfr.#: TSB41LV06

    OMO.#: OMO-TSB41LV06-1190

    		 Nuevo y original
    TSB41LV06A

    Mfr.#: TSB41LV06A

    OMO.#: OMO-TSB41LV06A-1190

    		 Nuevo y original
    TSB41LV06PZT

    Mfr.#: TSB41LV06PZT

    OMO.#: OMO-TSB41LV06PZT-1190

    		 Nuevo y original
    TSB41LV03APFP

    Mfr.#: TSB41LV03APFP

    OMO.#: OMO-TSB41LV03APFP-TEXAS-INSTRUMENTS

    		 1394 Interface IC THREE-PORT CABLE XCVR/ARBITER
    TSB41LV04APFP

    Mfr.#: TSB41LV04APFP

    OMO.#: OMO-TSB41LV04APFP-TEXAS-INSTRUMENTS

    		 1394 Interface IC Four-Port Cable Xcvr/Arbite
    TSB41LV06APZP

    Mfr.#: TSB41LV06APZP

    OMO.#: OMO-TSB41LV06APZP-TEXAS-INSTRUMENTS

    		 1394 Interface IC Six-Port Cable Xcvr/Arbite
    Disponibilidad
    Valores:
    78
    En orden:
    2061
    Ingrese la cantidad:
    El precio actual de TSB41LV06APZP es solo de referencia, si desea obtener el mejor precio, envíe una consulta o envíe un correo electrónico directo a nuestro equipo de ventas [email protected]
    Empezar con
    Nuevos productos
    More Newest Products
    Top