DC1795A

DC1795A
Mfr. #:
DC1795A
Fabricante:
Analog Devices Inc.
Descripción:
Clock & Timer Development Tools LTC6950 Demo - Integer-N PLL with 5 outp
Ciclo vital:
Nuevo de este fabricante.
Ficha de datos:
DC1795A Ficha de datos
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Más información:
DC1795A más información DC1795A Product Details
Atributo del producto
Valor de atributo
Fabricante:
Analog Devices Inc.
Categoria de producto:
Herramientas de desarrollo de temporizador y reloj
RoHS:
Y
Producto:
Tableros de demostración
Escribe:
Sintetizadores PLL / Multiplicadores / Divisores
La herramienta es para la evaluación de:
LTC6950
Frecuencia:
1 GHz
Descripción / Función:
Circuito de demostración para un PLL de bajo ruido y baja fluctuación con distribución de reloj
Serie:
LTC6950
Marca:
Dispositivos analógicos
Tipo de interfaz:
USB
Para usar con:
LTC6950
Voltaje de suministro operativo:
3.3 V
Tipo de producto:
Herramientas de desarrollo de temporizador y reloj
Cantidad de paquete de fábrica:
1
Subcategoría:
Herramientas de desarrollo
Tags
DC179, DC17, DC1
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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we buy and manage excess electronic components, including excess inventory identified for disposal.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***va Crawler
LTC6950 Demo Board| Integer-N PLL with 5 outputs (requires DC590 or DC2026)
***ical
LTC6950 Clock Generator and Synthesizer Evaluation Board
***ark
Demo Board, 1.4Ghz Pll W/ Clk Dist
***log Devices
The LTC6950 is a low phase noise integer-N frequency synthesizer core with clock distribution. The LTC6950 delivers the low phase noise clock signals demanded in high frequency, high resolution data acquisition systems. The frequency synthesizer contains a full low noise PLL core with a programmable reference divider (R), a programmable feedback divider (N), a phase/frequency detector (PFD) and a low noise charge pump (CP). The clock distribution section of the LTC6950 delivers up to five outputs based on the VCO input. Each output is individually programmed to divide the VCO input frequency by any integer from 1 to 63 and to delay the output by 0 to 63 VCO clock cycles. Four of the outputs feature very low noise, low skew LVPECL logic signals capable of operation up to 1.4GHz. The fifth output is selectable as either an LVDS (800MHz) or CMOS (250MHz) logic type. This output is also programmed to produce an output signal based on either the VCO input or the reference divider output. Applications Clocking High Speed, High Resolution ADCs, DACs and Data Acquisition Systems Low Jitter Clock Generation and Distribution
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BOARD DEMO USB SERIAL CONTROLLER
Disponibilidad
Valores:
Available
En orden:
1989
Ingrese la cantidad:
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